technical data KK74HC166A 8-bit serial or parallel-input/ serial-output shift register high-performance silicon-gate cmos ordering information kk 74hc166an plastic kk 74hc166ad soic t a = -55 t o 125 c for all packages the kk 74hc166a is identical in pinout to the ls/als166. the devi ce i nput s are com p at i b l e wi t h st andard c m os out put s; wi t h pul l up resistors, they are com p a tible with ls/alsttl outputs. th is d e v i ce is a p a rallel-in o r serial-in , serial-o u t sh ift reg i ster with gated clock inputs and an overriding clear input . the shift/load input est a bl i s hes t h e paral l e l - i n or seri al -i n m ode. w h en hi gh, t h i s i nput enabl e s t h e seri al dat a i nput and coupl es t h e ei ght fl i p -fl ops for seri al shi f t i ng with each clock pulse. synchronous lo ading occurs on the next clock pul se when t h i s i s l o w and t h e paral l e l dat a i nput s are enabl e d. seri al dat a fl ow i s i nhi bi t e d duri ng paral l e l l o adi ng. c l ocki ng i s done on t h e l o w-t o - high level edge of the clock pulse via a two input positive nor gate, whi c h perm i t s one i nput t o be used as a cl ock enabl e or cl ock i nhi bi t funct i on. c l ocki ng i s i nhi bi t e d when ei t h er of t h e cl ock i nput s are hel d high, holding either input low enable s the other clock input. this will al l o w t h e sy st em cl ock t o be free runni ng and t h e regi st er st opped on com m a nd wi t h t h e ot her cl ock i nput . a change from l o w-t o -hi gh on t h e cl ock i nhi bi t i nput shoul d onl y be done when t h e cl ock i nput i s hi gh. a buffered di rect cl ear i nput overri des al l ot her i nput s, i n cl udi ng t h e cl ock, an d s ets all flip -flo p to zero . pin assignment ? outputs directly interf ace to cmos, nmos, and ttl ? operat i ng vol t a ge r a nge: 2.0 t o 6.0 v ? low input c u rrent : 1.0 a ? high noise im m unity characteristic of cmos devices logic diagram pin 16 =v cc pin 8 = gnd 1
KK74HC166A maximum ratings * sym b o l p a r a m e t e r valu e un i t v cc dc suppl y vol t a ge (referenced t o gnd) -0.5 t o +7.0 v v in dc input vol t a ge (referenced t o gnd) -1.5 t o v cc +1.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input c u rrent , per pi n 20 ma i out dc out put c u rrent , per pi n 25 ma i cc dc suppl y c u rrent , v cc and gnd pins 50 ma p d po wer dissip a tio n in still air, plastic dip+ soic package+ 750 500 mw tst g st orage tem p erat ure -65 t o +150 c t l lead tem p erat ure, 1 m m from c a se for 10 seconds (plastic dip or soic package) 260 c * m a xi m u m r a t i ngs are t hose val u es bey ond whi c h dam a ge t o t h e devi ce m a y occur. functional operation should be restricted to the reco m m e nded operating conditions. +derat i ng - pl ast i c dip: - 10 m w / c from 65 t o 125 c soic package: : - 7 m w / c from 65 t o 125 c recommended operating conditions sy m bol p a r a m e t e r m i n m a x uni t v cc dc suppl y vol t a ge (referenced t o gnd) 2.0 6.0 v v in , v out dc input vol t a ge, out put vol t a ge (referenced t o gnd) 0 v cc v t a operat i ng tem p erat ure, al l package ty pes -55 +125 c t r , t f input r i se and fal l ti m e (fi gure 1) v cc =2.0 v v cc =4.5 v v cc =6.0 v 0 0 0 1000 500 400 ns thi s devi ce cont ai ns prot ect i on ci rcui t r y t o guard agai ns t dam a ge due t o hi gh st at i c vol t a ges or el ect ri c fi el ds. however, precautions m u st be taken to avoid applications of any voltage highe r than m a xim u m rated voltages to this hi gh-i m pedance ci rcui t . for proper operat i on, v in and v out shoul d be const r ai ned t o t h e range gnd (v in or v out ) v cc . unused i nput s m u st al way s be t i e d t o an appropri a t e l ogi c vol t a ge l e vel (e.g., ei t h er gnd or v cc ). unused out put s m u st be l e ft open. 2
KK74HC166A dc electrical characteristics (voltages referenced to gnd) v cc guaranteed lim it sy m bol p a r a m e t e r test c ondi t i o n s v 25 c to -55 c 85 c 125 c un it v ih m i ni m u m hi gh- level input vol t a ge v out =0.1 v or v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 v v il m a x i mu m l o w - level input vol t a ge v out =0.1 v or v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 v v oh m i ni m u m hi gh- level out put vol t a ge v in =v ih or v il ? i out ? 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in =v ih or v il ? i out ? 4.0 m a ? i out ? 5.2 m a 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 v ol m a x i mu m l o w - level out put vol t a ge v in =v ih or v il ? i out ? 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in =v ih or v il ? i out ? 4.0 m a ? i out ? 5.2 m a 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 i in m a xi m u m input leakage current v =v cc or gnd 6.0 0.1 1.0 1.0 a i cc m a x i mu m q u i e s c e n t suppl y c u rrent (per package) v in =v cc or gnd i out =0 a 6.0 8 . 0 8 0 1 6 0 a function table input s i n t e rnal out put s out put c l e a r s h i f t / l o a d c l o c k inhi bi t c l o c k s a parallel a...h q a q b q h l x x x x x l l l h x x x x n o c h a n g e h l l x a . . . h a b h h h l h x h q an q gn h h l l x l q an q gn h x h x x x n o c h a n g e x = don?t care a...h = the level of steady state input voltage at input a trough h respectively 3
KK74HC166A ac electrical characteristics (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed lim it sym b o l p a r a m e t e r v 25 c to -55 c 85 c 125 c unit f ma x m i ni m u m c l ock frequency (50% dut y c y cl e) (fi gures 2 and 4) 2.0 4.5 6.0 6.0 31 36 5.0 25 28 4.2 21 25 mh z t plh , t phl m a xi m u m propagat i on del a y , c l ock (or c l ock in h i b it) to q h (fi gures 2,3 and 4) 2.0 4.5 6.0 140 28 24 175 35 30 210 42 36 ns t phl m a xi m u m propagat i on del a y , c l ear t o q h (fi gures 1 and 4) 2.0 4.5 6.0 150 30 26 200 40 34 230 48 40 ns t tlh , t thl m a xi m u m out put transi t i on ti m e , any out put (fi gures 1 and 4) 2.0 4.5 6.0 75 16 14 95 20 18 110 25 20 ns c in m a xi m u m input c a paci t a nce - 10 10 10 pf power dissipation capacitance (per package) typical @25 c,v cc =5.0 v c pd used t o det e rm i n e t h e no-l o ad dy nam i c power consum pt i on: p d =c pd v cc 2 f+i cc v cc 1 4 0 p f timing requirements (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed lim it sym b o l p a r a m e t e r v 25 c to -55 c 85 c 125 c un it t su m i ni m u m set up ti m e , shi f t / l oad t o c l ock (fi gure 3) 2.0 4.5 6.0 80 16 14 100 20 18 120 24 20 ns t su m i ni m u m set up ti m e , dat a before c l ock (or c l ock inhi bi t ) (fi gure 3) 2.0 4.5 6.0 80 16 14 100 20 18 120 24 20 ns t w m i ni m u m pul s e w i dt h, c l ock (or c l ock inhi bi t ) (fi gure 2) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns 4
KK74HC166A fi gure 1. sw i t chi n g waveforms fi gure 2. sw i t chi n g waveforms fi gure 3. sw i t chi n g waveforms figure 4. test circuit 5
KK74HC166A timing diagram expanded logic diagram 6
KK74HC166A n s u f f i x p l as t i c di p (m s - 0 0 1 b b ) sy m b o l m i n m a x a 18. 67 19. 69 b 6. 1 7 . 1 1 c 5. 33 d 0. 36 0. 56 f 1. 14 1. 78 g h j 0 10 k 2. 92 3. 81 no t e s : l 7. 62 8. 26 1. d i m e n s i o n s ?a ?, ?b ? d o n o t i n cl u d e m o l d f l as h o r p r o t r u s i o n s . m 0. 2 0 . 3 6 m a x i m u m m o l d f l a s h o r p r o t r u s i o n s 0. 25 m m ( 0 . 010) p e r s i d e . n 0. 38 d su f f i x so i c (m s - 0 1 2 a c) sy m b o l m i n m a x a 9. 8 1 0 b 3. 8 4 c 1. 35 1. 75 d 0. 33 0. 51 f 0. 4 1 . 2 7 g h j 0 8 no t e s : k 0. 1 0 . 2 5 1. d i m e n s i o ns a a n d b d o no t i n c l ud e m o l d f l a s h o r p r ot r u s i on . m 0. 19 0. 25 2. m a x i m u m m o l d f l a s h o r p r o t r u s i o n 0. 15 m m ( 0 . 006) p e r s i d e p 5. 8 6 . 2 fo r a ; fo r b ? 0. 25 m m ( 0 . 010) p e r s i d e . r 0. 25 0. 5 5. 72 2. 54 7. 62 1. 27 d i me n s i o n , mm d i me n s i o n , mm a b h c k c m j f m p g d r x 4 5 se a t i n g pl an e 0 . 25 ( 0 . 010 ) m t -t - 1 16 8 9 l h m j a b f g d se a t i n g pl a n e n k 0. 2 5 ( 0 . 010) m t -t - c 1 16 8 9 7
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